The relentless pursuit of faster and more energy-efficient computing has hit a physical barrier in conventional transistors. But a research team at The Hong Kong Polytechnic University (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) using 2D nanomaterials, potentially unlocking a new era of ultra-low-power electronics essential for next-generation AI chips.
Traditional transistors rely on thermionic emission, requiring a minimum gating voltage of 60 millivolts (mV). This constraint, known as the 'Boltzmann limit,' makes subthreshold swing (SS) values below 60 mV per decade physically impossible at room temperature, capping the energy efficiency of integrated circuits. The new TFET, however, circumvents this limit by employing quantum tunnelling, a mechanism where charge carriers pass through an energy barrier rather than over it.
Led by Prof. Jianhua HAO, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, the collaborative research involved the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The findings were published in the prestigious journal Science.
Prof. Hao explained, 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.'
The team created an ultra-thin heterostructure of alternating 2D bismuth and indium selenide layers using pulsed laser deposition. Through precise control of the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in its 2D form, enabling efficient tunnelling of charge carriers into indium selenide. This design allowed the TFET to achieve SS values well below the 60 mV per decade limit while operating at room temperature on silicon substrates. The device required a gate-voltage range of only 160 mV, far lower than the 800 mV typically needed in conventional transistors.
Notably, the TFET resolved a longstanding challenge in experimental TFETs by delivering a high output current alongside an exceptionally high ON/OFF current ratio. This balance is critical for driving multiple downstream logic gates and minimizing circuit delay, making the device practical for real-world applications.
The implications are significant. As the semiconductor industry faces physical limits with current transistor technology, this breakthrough offers a viable path to continue scaling performance while reducing power consumption. The ability to operate at low voltages is particularly crucial for AI chips, which require massive parallel processing and are constrained by energy budgets. With further development, this TFET could become a foundational component of future computing systems, enabling more powerful and efficient devices.
